The present invention relates to integrated circuit devices and methods of manufacturing the same, and more particularly to gate all-around devices with a gate electrode encircling a channel region and methods of manufacturing the same.
Integrated circuit (semiconductor) devices, such as field effect transistors, are widely used in logic, memory, processor and other integrated circuit devices. As is well known to those having skill in the art, an integrated circuit field effect transistor includes spaced apart source and drain regions, a channel therebetween and a gate electrode adjacent the channel. Integrated circuit field effect transistors are often referred to as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply as MOS devices. Although these terms will be used in the present application, they are used to generally denote integrated circuit field effect transistors and are not limited to field effect transistors having metal gates or oxide gate insulators.
As the integration density of integrated circuit field effect transistors continues to increase, the size of the active region and the channel length may continue to decrease. With the reduction in the channel length of the transistor, the influence of the source/drain upon the electric field or potential in the channel region may become considerable. This is typically called the “short channel effect.” Further, with the scaling down of the active size, the channel width typically decreases, which may increase a threshold voltage. This is generally called the “narrow width effect”.
In order to limit or prevent the short channel effect, various types of FETs have been proposed. Examples of transistor device designs directed to the short channel effect in highly integrated devices include a recessed channel array transistor (RCAT), a fin-shaped FET (FinFET) and a gate-all-around transistor (GAAT). These types of FETs are described, for example, in U.S. Patent Application No. 2004/0063286.
However, a GAAT typically has a gate electrode formed using a contact-shaped pattern or bar-shaped pattern. As design rules are being decreased, it may be difficult to fabricate such contact-shaped or bar-shaped gate electrodes on an integrated circuit (semiconductor) substrate. Moreover, an overlap margin may not be sufficiently secured during photolithography operations used when forming the gate electrode. In addition, a leakage current between the substrate and the source/drain regions may not be sufficiently limited.